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GLT41116
64k x 16 CMOS Dynamic RAM with Fast Page Mode
FEATURES
x 65,536 words by 16 bits organization. x Fast access time and cycle time. x Dual CAS input. x Low power dissipation. x Read-Modify-Write, RAS-Only Refresh, CAS-before-RAS Refresh, Hidden Refresh and Test Mode Capability. x 256 refresh cycles per 4ms. x Available in 40-Pin 400 mil SOJ, and 40/44-Pin TSOP (Type II). x Single 5.0V 10% Power Supply. x All inputs and Outputs are TTL compatible. x Fast Page Mode operation.
GENERAL DESCRIPTION
The GLT41116 is a 65,536 x 16 bit high-performance CMOS dynamic random access memory. The GLT41116 offers Fast Page mode, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41116 has symmetric address and accepts 256-cycle refresh in 4ms interval. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256x16 bits, within a page, with cycle times as short as 18ns. The GLT41116 is best suited for graphics, and DSP applications requiring high performance memories.
July 1998 (Rev. 1)
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GLT41116
FUNCTIONAL BLOCK DIAGRAM
Column Decoder *** 256 *** Sense Amplifier Column Address Buffer A[7:0] Row Address Buffer X[7:0] Y[7:0] *** 256 x 16 *** Row Decoder x 16 DQ[7:0] x8 Data Input Buffer x8 x8 Data Output Buffer x8
*** 256 ***
Memory Array 256 x 256 x 16
x8
Data Output Buffer
x8 DQ[15:8]
VCC GND
CAS-before-RAS Counter
x8
Data Input Buffer
x8
RAS LCAS UCAS WE OE
Clock Generator
Lower Byte Control Upper Byte Control
Figure 1. GLT41116 64 x 16 CMOS
Signal Descriptions
Symbol A0 - A7 RAS UCAS LCAS WE OE DQ[15:0] VCC VSS NC Type Input Input Input Input Input Input Input Input Input Input Address Inputs Row address strobe Column address strobe/upper byte control Column address strobe/lower byte control Write enable Output enable Data inputs/outputs +5V power supply Ground No connection Description
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GLT41116
Truth Table
Function Stand By Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write Fast-Page Mode Read 1st Cycle 2nd Cycle Fast-Page Mode Write 1st Cycle 2nd Cycle Fast-Page Mode Read-Write 1st Cycle 2nd Cycle Hidden Refresh Read Write RAS-Only Refresh CBR Refresh
1. 2. 3. 4.
Address
RAS H
CASL HX L L H L L H L HL HL HL HL HL HL L L H L
CASH HX L H L L H L L HL HL HL HL HL HL L L H L
WE X H H H L L L HL H L L L HL HL H L X X
OE X l L L X X X LH L X X X LH LH L X X X
DQ High-Z Data Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z
Notes
Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Col Row/Col Col Row/Col Col Row/Col Row/Col Row
L L L L L L L L L L L L L LHL LHL L HL
[1] [2] [1] [1] [2] [2] [1] [2] [1] [2] [1] [2] [3]
[4]
These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). EARLY WRITE Only. At least one of the two CAS signals must be active (UCAS or LCAS).
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GLT41116
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Parameter Operating Temperature, TA (ambient) Storage Temperature (plastic) Voltage Relative to VSS Short Circuit Output Current` Power Dissipitation Rating -0C to +70C -55C to +125C -1.0V to +7.0V 50 mA 1.0 W
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance [1]
Symbol CIN1 CIN2 COUT Address Input RAS, LCAS, UCAS, WE, OE Data Input/Output Parameter Max 5 7 7 Units pF pF pF
1. Capacitance is sampled and not 100% tested
DC Characteristics (TA = 0C to 70C, VCC = 5V 10%, VSS = 0V, unless otherwise specified)
-30 Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE Standby Current, (TTL) Refresh Current, RASOnly Operating Current, EDO Page Mode Refresh Current, CASbefore-RAS Standby Current, (CMOS) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 4.2 mA IOH = -5 mA 2.4 Conditions 0V VIN 5.5V (All other pins not under test = 0V) 0V VOUT 5.5V Output is disabled (Hiz) tRC = tRC (min.) RAS, UCAS, LCAS at VIH other inputs VSS RAS cycling, UCAS, LCAS at VIH tRC = tRC (min.) RAS at VIL, UCAS, LCAS address cycling: tPC = tPC (min.) RAS, UCAS, LCAS address cycling: tRC = tRC (min.) RAS VCC -0.2V, UCS VCC -0.2V, LCAS VCC -0.2V, All other inputs VCC -1 2.4 Min -10 Max +10 +10 180 2 180 180 Min -10 -35 Max +10 +10 170 2 170 170 Min -10 -40 Max +10 +10 160 2 160 160 Min -10 -45 Max +10 +10 150 2 150 150 Units A A mA mA mA mA
[2] [1] [2]
Notes
[1] [2]
ICC5 ICC6
180 2
170 2
160 2
150 2
mA mA
[1]
VIL VIH VOL VOH
+0.8 VCC +1 0.4
-1 2.4
+0.8 VCC +1 0.4
-1 2.4
+0.8 VCC +1 0.4
-1 2.4
+0.8 VCC +1 0.4
V V V V
[3]
2.4
2.4
2.4
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC (max) is measured with a maximum of one transition per address cycle in random READ/WRITE and Fast-Page Mode. 3. Specified VIL (min) is steady state operation. During transitions VIL (min) may undershoot to -1.0V for a period not to exceed 20 ns. All AC parameter are measured with VIL (min) VSS and VIH (max) VCC.
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GLT41116
AC Characteristics (0 C TA 70 C, VCC = 5.0V 10%) [1]
-30 Parameter Read/Write Cycle Time Read Modify Write Cycle Time Access Time for RAS Access Time for CAS Access TIme from Column Address CAS to output ion Low-Z Output buffer turn-off delay from CAS Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS To RAS Precharge Time Row Address Setup TIme Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time Referenced to RAS Column Address Lead Time Referenced to RAS Read Command Setup Time Read Command Hold Time Referenced to RAS Read Command Hold Time Referenced to CAS WE Hold Time Referenced to CAS Write Command Hold time Referenced to RAS WE Pulse Width WE Lead Time Referenced to RAS WE Lead Time Referenced to CAS Data-In Setup Time Data-In Hold Time Data Hold Time Referenced to RAS WE Setup Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time CAS Setup TIme (CAS Before RAS Refresh) CAS Hold Time (CAS Before RAS Refresh) RAS to CAS Precharge Time CAS Precharge Time (CBR Counter Test Cycle) Access Time From CAS Precharge Fast Page Mode Read/Write Cycle Time Symbol tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCPRP tASR tRAH tASC tCAH tAR tRAL tRCS tRRH tRCH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tRWD tCWD tAWD tCSR tCHR tRPC tCPT tCPA tPC Min 65 80 - - - 0 3 3 25 30 10 30 10 13 10 5 0 6 26 15 26 15 0 0 0 6 26 6 10 10 0 7 27 0 47 24 29 5 10 5 20 - 18 Max - - 30 10 15 - 8 50 - 100k - - 10k 20 15 - - - - - - - - - - - - - - - - - - - - - - - - - - 18 - Min 70 99 - 11 - 0 3 3 25 35 12 36 12 17 12 5 0 6 30 18 30 18 0 0 0 6 30 6 11 11 0 6 31 0 58 29 36 5 10 5 20 - 21 [2] -35 Max - - 35 - 18 - 8 50 - 100k - - 10k 24 17 - - - - - - - - - - - - - - - - - - - - - - - - - - 21 - Min 75 105 - 12 - 0 3 3 25 40 12 40 12 18 13 5 0 6 34 20 34 20 0 0 0 6 34 6 12 12 0 8 36 0 63 30 38 5 10 5 20 - 23 -40 Max - - 40 - 20 - 8 50 - 100k - - 10k 28 20 - - - - - - - - - - - - - - - - - - - - - - - - - - 23 - Min 80 110 - - - 0 3 3 25 45 13 46 13 18 12 5 0 6 39 23 39 23 0 0 0 6 39 6 12 12 0 8 41 0 68 30 40 5 10 5 20 - 25 -45 Max - - 45 12 22 - 8 50 - 100k - - 10k 33 23 - - - - - - - - - - - - - - - - - - - - - - - - - - 25 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
[3] [10] [10] [11] [9] [9] [9] [9] [7] [7] [8] [9] [8] [4] [4] [6] [3] [4] [3] [4] [3] [4] [3] [5] [2]
Notes
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July 1998 (Rev. 1)
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GLT41116
AC Characteristics (0 C TA 70 C, VCC = 5.0V 10%) [1]
-30 Parameter Fast Page Mode Read Modify Write Cycle Time CAS Precharge Time (Fast Page Mode) RAS Pulse Width (Fast PAge Mode) RAS Hold Time From CAS Precharge Access Time From OE OE to Delay Time Output Buffer Turn-off Delay Time From OE OE Hold Time WE Hold Time (Hidden Refresh Cycle) Refresh Time (256 Cycles) Symbol tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWHR tREF Min 48 6 30 25 - 8 3 6 15 - Max - - 100k - 10 - - - - 4 Min 60 6 35 25 - 8 3 6 15 - [2] -35 Max - - 100k - 11 - 8 - - 4 Min 53 7 40 25 - 8 3 7 15 - -40 Max - - 100k - 12 - 8 - - 4 Min 65 7 45 30 - 8 3 7 15 - 4 -45 Max - - 100k - 12 - 8 - Units ns ns ns ns ns ns ns ns ns ms
[5]
Notes
1. An initial pause of 100 s is required after power-up followed by any 8 RAS only Refresh or CAS before RAS Refresh Cycles to initialize the internal circuit. 2. VIH (min) and VIL (min) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max), AC measurements assume tT = 3 ns. 3. Measured with an equivalent to 2 TTL loads and 100 pF. 4. For read cycles, the access time is defined as follows:
Input Conditions tRAD tRAD (max.) and tRCD tRCD (max.) tRAD (max.) < tRAD and tRCD tRCD (max.) tRCD (max). < tRCD Access Time tRAC (Max.) tAA (Max.) tCAC (Max.)
tRAD (max.) and tRCD (max.) indicate the points which the access time changes and are not the limits of operation. tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to VOH or VOL. tCRP (min.) requirement should be applicable for RAS, CAS cycle preceded by any cycles. Either tRCH (min.) or tRRH (min) must be satisfied for a read cycle. tWP (min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH (min.) should be satisfied. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD tCWD (min.), tRWD tRWD (min.) and tAWD tAWD (min.), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 10. This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write orr read modify write cycles. 11. tAR, tWCR, and tDHR are referenced to tRAD(max.). 5. 6. 7. 8. 9.
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1 CLK tKHKL tEVKH CKE tKHEX tKLKH 2 tKHKH 3 4 5 6 7 8 9 10
tCVKH CE
tKHCX
ADV/LD
R/W
BWn
tAVKH ADDRESS A1
tKHAX A2 A3 tKHQV tDVKH tKHDX D (A1) D (A2) tKHQX1 D (A2+1) Q (A3) tKHQX Q (A4) tGHQZ A4 tGLQV A5 tKHQZ Q (A4+1) tGLQX tKHQX D (A5) D (A6) D (A7) A6 A7
D/Q
OE
WRITE D(A1)
WRITE D(A2)
BURST WRITE D(A1+1)
READ Q(A3)
READ Q(A4)
BURST READ Q(A4+1)
WRITE D(A5)
READ Q(A6)
WRITE D(A7)
DESELECT
Don't Care NOTE: 1. For this waveform, ZZ is tied LOW. 2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
Undefined
Figure 2. Read/Write Timing
G-LINK Technology
July 1998 (Rev. 1)
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GLT41116
1 CLK 2 3 4 5 6 7 8 9 10
CKE
CE
ADV/LD
R/Wn
BWn
ADDRESS
A1
A2
A3
A4
A5 tKHQZ tKHQX
D/Q WRITE D(A1) READ Q(A2) STALL
D (A1) READ Q(A1)
Q (A2) WRITE D(A2) STALL
Q (A3) NOP
D (A4) READ Q(A3) DESELECT
D (A5) Continue DESELECT Undefined
Don't Care NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE being used to create a "pause." A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
Figure 3. NOP, STALL and DESELECT Timing
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GLT41116
PACKAGING INFORMATION
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS
Top View
Figure 4. 40-Pin 400 mil Plastic SOJ Pin Assignment
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9 10 Top View
44 43 42 41 40 39 38 37 36 35
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8
NC NC WE RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE NC A7 A6 A5 A4 VSS
Figure 5. 44/40-Pin 400 mil TSOP (TypeII) Pin Assignment
G-LINK Technology
July 1998 (Rev. 1)
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GLT41116
SEATING PLANE 0.95 TYP 1 40
26.03 0.13 20
21
10.16 0.13 11.17 0.13
1.27 0.81 MAX. +0.07 0.43 -0.05
0.18
M
3.6 0.25 2.35 TYP 0.65 MIN. 0.2 -0.05
+0.07
9.3 0.25
Dimensions in millimeters
Figure 6. 40-Pin 400 mil SOJ Package Dimensions
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July 1998 (Rev. 1)
GLT41116
18.41 0.1 44 23
A
11.76 0.2 10.1 0.1
10.76 0.2
1 0.81 TYP 0.37
+0.08 -0.07
22 0.16
M
0.05 ~ 0.25 0.95 0.05 0.17 0.05 1.2 MAX Detail A
0.5 0.1 0.8 0.2
0.8
SEATING PLANE Dimensions in Inches (millimeters)
Figure 7. 40/44-Pin TSOP (Type II) Package Dimensions
G-LINK Technology
July 1998 (Rev. 1)
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GLT41116
ORDERING INFO
Part Number GLT4116-30J4 GLT4116-35J4 GLT4116-40J4 GLT4116-45J4 GLT4116-30TC GLT4116-35TC GLT4116-40TC GLT4116-45TC Speed 30 ns 35 ns 40 ns 45 ns 30 ns 35 ns 40 ns 45 ns Power Normal Normal Normal Normal Normal Normal Normal Normal Feature FPM FPM FPM FPM FPM FPM FPM FPM Package 40-Pin 400 mil SOJ 40-Pin 400 mil SOJ 40-Pin 400 mil SOJ 40-Pin 400 mil SOJ 44-Pin 400 mil TSOP 44-Pin 400 mil TSOP 44-Pin 400 mil TSOP 44-Pin 400 mil TSOP
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Notes:
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GLT41116
Notes:
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GLT41116
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(c) 2001 G-LINK Technology All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology. Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given. G-LINK Technology reserves the right to change products or specifications without notice. The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for G-LINK applications assistance, customer's product design, or infringement of patents arising from use of semiconductor devices in such systems' designs. Nor does G-LINK warrant or represent that any patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. G-LINK Technology's products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for surgical implant into the human body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause significant injury to the user in the event of failure. The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies. Printed in USA

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